Title:  Verify the Verifier via SVUnit

Abstract: Verification teams don't typically verify testbench components. But this Qualcomm Technologies IP team realized the necessity of unit testing a critical testbench component and the corresponding debug time and frustration it could prevent for downstream IP and chip teams.

This experience report documents the team's first time unit testing with SVUnit, from start to finish. We discuss the justification made with managers to have engineers assigned, how to pick the right test subject to ensure a positive outcome, the method used for verifying testbench checkers, component defect rate, framing unit testing and the defects found as opportunities for improvement and lessons learned for long term maintenance

Date: 7th April 2020

Timing: 

India: 21:00 to 22:00, Austin, USA: 10:30am to 11:30am, Boston, USA: 11:30am to12:30pm

Sanjose, USA: 8:30am to 9:30am, Munich, Germany: 17:30 to 18:30, Israel: 18:30 to 19:30

Registration: https://docs.google.com/forms/d/1gEcWkvw5CRkxio26ysv7AOLuVPv_z1FJi_HmnGuBrpE/viewform?edit_requested=true

WebEx Meeting Link: https://venkatsri.my.webex.com/meet/venkatsri

TRAINERS PROFILE

Srinivasan Venkatramanan

http://www.linkedin.com/in/svenka3

· Over 20+ years of experience in VLSI Design & Verification

· Designed, verified and lead several multi-million ASICs in image processing,

networking and communication domain

· Worked at Philips, Intel, and Synopsys in various capacities. Co-authored leading

books in the Verification domain.

· Presented papers, tutorials in various conferences, publications and avenues.

· Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV and

OOP for Verification

· Holds M.Tech in VLSI Design from prestigious IIT, Delhi.

Ajeetha

http://www.linkedin.com/in/ajeetha

· Has 18+ years of experience in Verification

· Implemented, architected several verification environments for block &

subsystems

· Co-authored leading books in the Verification domain.

· Presented papers, tutorials in various conferences, publications and avenues.

· Has worked with all leading edge simulators and formal verification (Model

Checking) tools.

· Conducted workshops and trainings on PSL, SVA, SV, OVM, E, ABV, CDV and

OOP for Verification

· Holds M.S.E.E. from prestigious IIT, Madras.